I have made a extension to the original FPGA-Software from James. For access to the raw data from the ADC, there is now inserted a new 16K*14Bit RAM. Now the HiQSDR can also used as wideband spectroscop or as oszilloscop. This FPGA image is full compatible to version 1.1 from jams. Access to the raw ram data is independent to the other functions, so spectroscop and quisk can run parallel.
FPGA

Protocol


To start sampling raw data, send "bb" to UDP-Port 48250. Sampling stops automatically then the ram is full. To read the samples, send the start address to the same port. The answer is a packet with 1442 byte. First byte is a sequence number, first bit of second byte is a ready bit. This will cleared, then sampling starts and set if ram is full and sampling stops. This two header bytes follow 1440 bytes with 720 samples a 16 bit. For read the next segments from ram, send new requests with incremented start address. After reading the samples send new "bb" to the HiQSDR to start next sampling. For details have a look at the hiqscope source.

HiQScope


HiQScope is a simple application to demonstrate the fpga extension. This image, created with HiQScope, shows the full spectrum from 0 to 61 MHz over night.

HiQScope

Here is the full resolution Image (8192*4096) 38MB !.

Version 1.3-sg2 supported extended sample rates from 9600 up to 3840000 and is compatible to older versions. Sample rates above 960000 using reduced data width. In 16 Bit mode only MSB bit 23:8 transfered, in 8 bit mode only bit 15:8. In 8 bit mode use the attenuator to avoid clipping. Bit 7:6 in byte 12 from rx-ctl packet select transfer width and prescaler:

0: prescaler:8, width: 24 bit (compatible with older versions)
1: prescaler:2, width: 16 bit,
2: prescaler:40, width 24 bit
3: prescaler 2: width 8 bit

In bits 5:0 now prescaler values 2,3,4,5,6,7,8,9,10,16,20,32 and 40 supported. For details look at gr-hiqsdr source.

For wideband digital experiments version 1.3-sg3 also supports transmit rates up to 960k. Bit 5:4 in byte 11 select the rate:

0: 48k (compatible with older versions)
1: 192k
2: 480k
3: 8k

Download


FPGA-1.3-sg9: GPIO-Module support via SPI
FPGA-1.3-sg8: support for adaptive digital predistortion
FPGA-1.3-sg7: support for noice blanker
FPGA-1.3-sg6: initial filter changed, PIN 56 is output hi, tx-filter with 512 taps, clean tx clock
FPGA-1.3-sg5: raw output from cic filters, reduced dc error, tx delay for cw
FPGA-1.3-sg4: rx and tx fir-filter now complex and coefficients are loadable at runtime
FPGA-1.3-sg3: extended rx+tx rates
FPGA-1.3-sg2: extended rx rates
FPGA-1.3-sg1.1: Bugfix for Version FPGA-1.3-sg1
FPGA-1.3-sg1: has some problems in VNA-mode
FPGA-1.2-sg1
FPGA-1.1-sg1
HiQScope (linux binary)
HiQScope (windows setup)
HiQScope (src)

DL2STG